FIG. 1 illustrates in block diagram form a microprocessor 10 coupled to memory device 12 via data bus 14. Although not shown, data bus 14 includes a plurality of conductive lines, each one of which is capable of transmitting a data bit signal between memory device 12 and microprocessor 10. Microprocessor 10 includes a plurality of input/output (IO) devices (not shown in FIG. 1) coupled to respective conductive lines of data bus 14. IO devices generate the data bit signals which are subsequently transmitted over bus 14, or IO devices receive data bit signals generated by memory device 12 and transmitted via data bus 14.
IO devices include drivers for driving a conductive line of a bus in accordance with a data bit signal received by the IO device. FIG. 2A is a schematic diagram of a driver 16 which may be employed in one of the IO devices of microprocessor 10. IO driver 16 shown in FIG. 2A should not be considered prior art under 35 USC Section 102 to the invention described or claimed within this specification. In FIG. 2A, driver 16 includes a voltage level converter circuit 20, a pull-up circuit 22, and a pull-down circuit 24, all of which are coupled between input and output nodes 26 and 28. Operational aspects of voltage level converter circuit 20 are described in U.S. application Ser. No. 10/159,684.
Pull-up circuit 22 of FIG. 2A includes p-channel field effect transistors (FETs) 30 and 32 while pull-down circuit 24 includes N-channel FETs 40 and 42. FETs 32 and 42 are coupled to bias voltages Vp and Vn, respectively. FETs 32 and 42 limit the gate to source (Vgs) and gate to drain (Vgd) of FETS 30 and 32, respectively, below Vlimit as is more fully described in U.S. application Ser. No. 10/159,684.
Driver 16 receives input data bit signal Din 16 directly or indirectly from the core of microprocessor 10. In response to receiving Driver 16 generates output data bit signal Dout at output node 28 which, in turn, is directly or indirectly coupled to a conductive line of data bus 14. When driver 16 receives Din, voltage level converter 20 generates signal Dmod as is more fully described in U.S. application Ser. No. 10/159,684. The voltage magnitude of Dmod varies between VDD1, the voltage of a first power supply provided to driver 16, and an intermediate voltage Vint depending on the magnitude of Din. More particularly, voltage level converter circuit 20 generates Dmod equal to Vint when Din equals ground (logical 0), and voltage level converter circuit 20 generates Dmod equal to VDD1 when Din equals VDD2 (logical 1), the magnitude of a second power supply provided to the core of microprocessor 10. VDD1 is greater in magnitude that VDD2. Vint is between VDD1 and ground in magnitude, and Vint is at least a threshold voltage Vt below VDD1.
As noted, Dmod is generated as a function of Din. Dmod is provided to the gate of FET 30. When Dmod equals Vint, FET 30 switches on to create a conductive path between its source and drain. When switched on, current from the first power supply can pass through FET 30 and charge node 28 and the conductive line of bus 14 coupled thereto. Note that FET 32 is switched on and FET 40 is switched off when FET 30 is switched on. When Dmod equals VDD1, FET 30 is switched off and no current can flow therethrough. However, FET 40 is switched on to create a conductive path between its source and drain. When switched on, current from can pass through FET 40 to ground and discharge charge node 28 and the conductive line of bus 14 coupled thereto. Note that FET 42 is switched on when FET 40 is switched. Driver 16 thus generates Dout by charging or discharging output node 28 as a function of input data signal Din.
The signal frequency or rate at which output data bit signals Dout transmit over data bus 14 can limit the performance of the system shown in FIG. 1. The higher the transmission frequency, the better. The maximum frequency is a function not only of the time that it takes the electromagnetic wave fronts of data bit signal Dout to propagate on bus 14 between microprocessor 10 and memory device 12, but also the time required for data bit signal Dout to settle to a voltage level that can be reliably recognized by the receiving IO device of memory 12 as being high (logical 1) or low (logical 0).
The time required for Dout to settle is often referred to as the settling time. There are several factors which affect the settling time. For example, ringing due to reflections from impedance mismatches between the data bus 14 and drivers of IO devices connected thereto is a factor which affects the settling time of the signal.
FIG. 2B is current/voltage (IV) plot of pull-up circuit 22 of driver 16 at output node 28. This plot shows the impedance of the pull-up circuit 22 is zero from output voltage equal to zero to output voltage equal to V1; the impedance of pull-up circuit 22 varies from output voltage equal to V1 to output voltage equal to V2; the impedance of pull-up circuit 22 varies from output voltage equal to V2 to output voltage equal to VDD1, and; the impedance of pull-up circuit 22 varies for output voltages greater than VDD1. If driver 16 could be designed so that the impedance of driver 16 matches the impedance of the conductive line of data bus 14 coupled thereto, driver 16 would not be a source of signal ringing. However, the impedance of pull-up circuit 22 will mismatch the impedance of data bus 14. As such, the impedance of driver 16 will mismatch the impedance of data bus 14 for certain output voltages.
FIG. 3A is a schematic diagram of driver 16 with P channel FETS 34-36 and N channel FETs 44-48 added thereto. IO driver 16 shown in FIG. 3A should not be considered prior art under 35 USC Section 102 to the invention described or claimed within this specification. Pull-up circuit 22 of FIG. 3A now includes two branches designated normal connected branch 52 and diode connected branch 54 through which output node 28 may be charged when Din equals ground. The normal connective branch includes P channel FETs 30 and 32 connected in series between VDD1 and output node 28, while the diode connected branch 54 includes P channel FETs 34-38 connected in series between VDD1 and output node 28. P channel FET 38 is configured as a diode.
The pull-up circuit 22 shown in FIG. 3A, unlike the pull-up circuit 22 shown in FIG. 2A, has a non-zero impedance at its output for a certain range of output voltages. FIG. 3B illustrates IV plots for the normal connected branch 52 and the diode connected branch 54. The plot for the diode connected branch 54 shows that the impedance of the diode connected branch 54 is constant for output voltages between zero and V1; the impedance of the diode connected branch 54 varies between output voltages V1 and V2; and the impedance of the diode connected branch 54 is zero for output voltages greater than V2. FIG. 3B also illustrates the IV plot for the pull-up circuit 22 in FIG. 3A. The IV plot for pull-up circuit 22 is the addition of the IV plots for the normal connected branch 52 and the diode connected branch 54. In FIG. 3B, the pull-up circuit IV plot is linear between ground and V2. As such, the impedance for pull-up circuit 22 is a non-zero constant between output voltages equal to ground and V2. However, due to the influence of the normal connected branch, the IV plot is nonlinear for output voltages which exceed V2. In other words, the impedance of the pull-up circuit 22 shown in FIG. 3B varies for output voltages which exceed V2. As such, the impedance of driver 16 shown in FIG. 3A will mismatch the impedance of data bus 14 at least for output voltages that exceed V2.
Disclosed is an input/output (IO) device having a power supply node, an input node for receiving an input data signal, and an output node for outputting an output data signal generated in response to the input node receiving the input data bit signal. The IO device also includes a pull-up driver coupled to the power supply node and the output node, wherein the pull-up driver comprises an impedance at the output node which is constant for all voltages at the output node. Additionally, the IO device may have a circuit coupled to the input node, the pull-up driver, and the output node. This circuit is configured to generate a signal that is provided to the pull-up driver. The signal generated by the circuit varies as a function of the voltage at the output node.
In one embodiment, the pull-up driver includes first and second p-channel field effect transistors (FETs). The drain of the first p-channel FET is coupled to the source of the second p-channel FET, the source of first p-channel FET is coupled to the power supply node, the drain of the second p-channel FET is coupled to the output node, the gate of the first p-channel FET is coupled to receive the signal generated by the circuit, and the gate of the second p-channel FET is coupled to a p-channel bias voltage node.
In one embodiment, the circuit includes first, second and third n-channel FETs and a p-channel FET. The source and drain of the first and second n-channel FETs are coupled together, the sources of the second n-channel FET and the p-channel FET are coupled together, the drains of the p-channel FET and the third n-channel FET are coupled together and to the pull-up driver, the source of the third n-channel FET is coupled to the input node, the gates of the first and third n-channel FETs are coupled to an n-channel bias voltage node, the gate of the second n-channel device is coupled to the output node, and the gate of the p-channel FET is coupled to a p-channel bias voltage node.